Chip-scale package and carrier for use therewith

ABSTRACT

A carrier for use in a chip-scale package includes a film with at least one aperture defined therethrough. The aperture, which is alignable with a corresponding bond pad of a semiconductor device over which the carrier is to be positioned, is at least partially filled with conductive material. A contact on a surface of the carrier may communicate with the conductive material within the aperture. A conductive bump may be disposed adjacent the contact. The carrier may be positioned on a semiconductor device to form a chip-scale package. Such a chip-scale package may include a semiconductor device invertedly disposed over the carrier with bond pads of the semiconductor device being substantially aligned with apertures of the carrier.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/309,665,filed Dec. 3, 2002, pending, which is a continuation of application Ser.No. 09/409,536, filed Sep. 30, 1999, now U.S. Pat. No. 6,521,995, issuedFeb. 18, 2003, which is a divisional of application Ser. No. 09/340,513,filed Jun. 28, 1999, now U.S. Pat. No. 6,228,687, issued May 8, 2001.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to carrier substrates for use inchip-scale packages and to chip-scale packages including such carriersubstrates. Particularly, the present invention relates to carriersubstrates fabricated from polymeric materials. Methods of fabricatingchip-scale packages are also within the scope of the present invention.

2. Background of Related Art

In conventional semiconductor device fabrication processes, a number ofdistinct semiconductor devices, such as memory chips or microprocessors,are fabricated on a semiconductor substrate, such as a silicon wafer.After the desired structures, circuitry, and other features of each ofthe semiconductor devices have been fabricated upon the semiconductorsubstrate, the substrate is typically singulated to separate theindividual semiconductor devices from one another.

Various post-fabrication processes, such as testing the circuits of eachof the semiconductor devices and burn-in processes, may be employedeither prior to or following singulation of the semiconductor substrate.These post-fabrication processes may be employed to impart thesemiconductor devices with their intended functionality and to determinewhether or not each of the individual semiconductor devices meetsquality control specifications.

The individual semiconductor devices may then be packaged. Along withthe trend in the semiconductor industry to decrease semiconductor devicesize and increase the density of structures of semiconductor devices,package sizes are also ever-decreasing. One type of semiconductor devicepackage, the so-called “chip-scale package” or “chip-sized package”(“CSP”), consumes about the same amount of real estate upon a substrateas the bare semiconductor device itself. Such chip-scale packagestypically include a carrier substrate having roughly the same surfacearea as the semiconductor device.

Some chip-scale packages include a semiconductor device and a polymericcarrier substrate. Exemplary chip-scale packages with polymeric carriersubstrates are disclosed in U.S. Pat. No. 5,677,576 (hereinafter “the'576 patent”), which issued to Masatoshi Akagawa on Oct. 14, 1997, U.S.Pat. No. 5,683,942 (hereinafter “the '942 patent”), which issued toKeiichiro Kata et al. on Nov. 4, 1997, and U.S. Pat. No. 5,844,304(hereinafter “the '304 patent”), which issued to Keiichiro Kata et al.on Dec. 1, 1998.

The '576 patent discloses a chip-scale package that includes asemiconductor device, a layer of insulative material, through which bondpads of the semiconductor device are exposed, disposed on an activesurface of the semiconductor device, and a conductive elastomer disposedadjacent the layer of insulative material and the bond pads of thesemiconductor device. Conductive elements are positioned adjacent theconductive elastomer so as to facilitate the disposition of a conductivebump that is laterally offset from the bond pad location. A photoresist,including apertures through which portions of the conductive elementsare exposed, is then disposed over the conductive elements and theconductive elastomer. Conductive bumps are disposed within the aperturesand in communication with the conductive elements. The carrier substrateand method of the '576 patent are somewhat undesirable because thedisposal of an additional layer of insulative material on the activesurface of the semiconductor device may increase fabrication time andcosts, as well as the likelihood of device failure. Moreover, as each ofthe bond pads is associated with a laterally extending conductiveelement, each of the conductive bumps is, somewhat undesirably,laterally offset from the location of its corresponding bond pad.

The '942 patent describes a carrier substrate including a polymer layerincluding conductive traces with raised contact pads disposed on a firstside thereof and corresponding conductive bumps disposed on the otherside thereof. The conductive traces and their corresponding conductivebumps communicate by means of electrically conductive vias through thecarrier substrate. A layer of insulative material is disposed upon theactive surface of the semiconductor device with which the carriersubstrate is to be assembled, laterally adjacent the bond pads. Thecarrier substrate, which is prefabricated, is disposed adjacent theactive surface of a semiconductor device by aligning the contact pads ofthe carrier substrate with the bond pads of the semiconductor device,disposing a quantity of adhesive material between the active surface andthe carrier substrate, and applying pressure to the carrier substrate toabut the contact pads against their corresponding bond pads. Pressure isapplied locally to the contact pads and, thus, to the bond pads throughapertures defined through the carrier substrate. The carrier substrateof the '942 patent is somewhat undesirable in several respects. Thedisposal of a layer of insulative material laterally adjacent the bondpads of the semiconductor device increases fabrication time and costs,as well as the likelihood of device failure. The semiconductor devicemay be damaged while localized pressure is applied to the bond padsthereof, again undesirably increasing the likelihood of device failureand, therefore, fabrication costs. Moreover, since the carrier substrateof the '942 patent is prefabricated, it is possible that the raisedcontact pads of the carrier substrate may not properly align with theircorresponding bond pads of the semiconductor device.

The polymeric carrier substrate of the '304 patent is fabricateddirectly upon an active surface of a semiconductor device. That carriersubstrate, however, does not include electrically conductive vias thatextend substantially longitudinally therethrough. Rather, a layer ofinsulative material is disposed on an active surface of a semiconductordevice upon which the carrier substrate is to be fabricated, adjacentthe bond pads thereof. Laterally extending conductive lines arefabricated on the layer of insulative material and in contact withcorresponding bond pads of the semiconductor device. Conductive bumpsare then disposed adjacent corresponding conductive lines and a layer ofpolymeric material applied to the semiconductor device so as to insulatethe conductive lines. The conductive bumps are exposed through the layerof polymeric material. Since each of the conductive lines of the carriersubstrate of the '304 patent extends substantially laterally from itscorresponding bond pad, each of the conductive bumps is, somewhatundesirably, laterally offset from the location of its correspondingbond pad. Moreover, the disposal of an additional layer of insulativematerial on the active surface of the semiconductor device, throughwhich the bond pads are disposed, increases fabrication time and costs,as well as the likelihood of device failure.

As the carrier substrate of such chip-scale packages is small,electrical connections between the semiconductor device and the carriersubstrate are often made by flip-chip-type bonds or tape-automatedbonding (“TAB”). Due to the typical use of a carrier substrate that hasa different coefficient of thermal expansion than the semiconductorsubstrate of the semiconductor device, these types of bonds may failduring operation of the semiconductor device.

Following packaging, the packaged semiconductor devices may be re-testedor otherwise processed to ensure that no damage occurred duringpackaging. The testing of individual packaged semiconductor devices is,however, somewhat undesirable since each package must be individuallyaligned with such testing or probing equipment.

Accordingly, there is a need for a chip-scale package with at least someconductive bumps or contacts that are not laterally offset from theposition of their corresponding bond pad and for a packaging method thatdoes not require the disposal of an additional layer of insulativematerial adjacent the active surface of the semiconductor device. Thereis also a need for a semiconductor packaging process that facilitatestesting, probing, and burn-in of semiconductor devices without requiringthe alignment of individual semiconductor devices and by which aplurality of reliable chip-scale packages may be substantiallysimultaneously assembled. An efficient chip-scale packaging process witha reduced incidence of semiconductor device failure is also needed.There is a further need for chip-scale packaged semiconductor devicesthat consume about the same amount of real estate as the semiconductordevices thereof and that withstand repeated exposure to the operatingconditions of the semiconductor device.

SUMMARY OF THE INVENTION

The present invention includes a chip-scale package (“CSP”) including asemiconductor device having at least one bond pad on an active surfacethereof and a carrier substrate, which is also referred to herein as acarrier, adjacent the active surface of the semiconductor device andincluding at least one electrically conductive via therethrough. The atleast one electrically conductive via preferably extends directlythrough or substantially longitudinally through the carrier substrateand is alignable with the at least one bond pad of the semiconductordevice. The carrier substrate may also include at least one conductivebump in communication with the at least one electrically conductive viaand disposed opposite the semiconductor device. The at least oneelectrically conductive bump may be disposed adjacent the at least oneelectrically conductive via. Alternatively, the carrier substrate maycarry at least one conductive trace that extends substantially laterallyfrom the at least one electrically conductive via. The at least oneconductive bump may be disposed in contact with the at least oneelectrically conductive trace and, therefore, the at least oneelectrically conductive bump may be laterally offset from itscorresponding bond pad of the semiconductor device.

Preferably, the carrier substrate comprises a layer of polymericmaterial, such as a polyimide. The polymeric material is preferablydisposed in a thickness or has a coefficient of thermal expansion thatwill not induce stress in the conductive links between the semiconductordevice and the carrier substrate under the operating conditions of thesemiconductor device (e.g., the operating temperature of thesemiconductor device). Accordingly, in accordance with the method of thepresent invention, the carrier substrate may be secured to the activesurface of the semiconductor device by disposing and spreading aquantity of polymeric material on the active surface of thesemiconductor device to a substantially consistent thickness.Alternatively, a preformed film of the polymeric material may be adheredor otherwise secured to the active surface of the semiconductor device.The layer of polymeric material may be disposed on the semiconductordevice either before or after the semiconductor device has beensingulated from a wafer.

Apertures may be defined through the layer of polymeric material byknown processes, such as by laser-drilling, by masking and etching, orby photoimaging the layer of polymeric material. These apertures may bedefined after the layer of polymeric material has been secured to theactive surface of the semiconductor device. Alternatively, if apreformed film of polymeric material is secured to the active surface ofthe semiconductor device, the apertures may also be preformed. If thelayer of polymeric material comprises a preformed film of polymericmaterial having preformed apertures therethrough, each aperture ispreferably substantially alignable with its corresponding bond pad ofthe semiconductor device as the polymeric film is secured to the activesurface of the semiconductor device.

A quantity of conductive material may be disposed in each aperture ofthe layer of polymeric material and, therefore, in contact with the bondpad that corresponds to the aperture. Each aperture and the quantity ofconductive material therein collectively define a conductive via of thecarrier substrate.

Conductive traces that extend substantially laterally from selected onesof the electrically conductive vias may also be fabricated on thecarrier substrate, opposite the semiconductor device. Preferably, theseconductive traces are positioned to laterally offset the locations ofcontacts or conductive bumps of the carrier substrate relative to thelocations of their corresponding bond pads of the semiconductor device.Accordingly, the conductive traces may impart the carrier substrate witha footprint that differs from that of the semiconductor device to whichthe carrier substrate is secured.

Conductive bumps may be disposed on a surface of the carrier substrateopposite the semiconductor device. Each conductive bump preferablycommunicates with at least one corresponding bond pad of thesemiconductor device. Accordingly, the conductive bumps may be disposedin contact with either an electrically conductive via or a substantiallylaterally extending conductive trace of the carrier substrate.

Other features and advantages of the present invention will becomeapparent to those of ordinary skill in the art through a considerationof the ensuing description, the accompanying drawings, and the appendedclaims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a cross-sectional representation of a first embodiment of achip-scale package according to the present invention;

FIG. 1A is a cross-sectional representation of another embodiment of achip-scale package according to the present invention;

FIG. 2 is a cross-sectional representation of a semiconductor devicehaving a layer of polymeric material secured to an active surfacethereof;

FIG. 2A is a cross-sectional representation of a semiconductor devicehaving a layer of polymeric material secured to an active surfacethereof and a quantity of polymeric material adjacent a peripheral edgethereof;

FIG. 2B is a schematic representation of a wafer including a pluralityof semiconductor devices thereon and a layer of polymeric materialdisposed over the active surfaces of the semiconductor devices;

FIG. 3 is a cross-sectional representation of the semiconductor deviceof FIG. 2, illustrating apertures defined through the layer of polymericmaterial;

FIG. 4 is a cross-sectional representation of the semiconductor deviceof FIG. 3, illustrating conductive material disposed within theapertures to form electrically conductive vias;

FIG. 4A is a cross-sectional representation of the semiconductor deviceof FIG. 4, illustrating substantially laterally extending conductivetraces in communication with the conductive material disposed inselected ones of the apertures, which conductive material formselectrically conductive vias;

FIG. 4B is a cross-sectional representation of the semiconductor deviceof FIG. 3, illustrating an alternative method of disposing conductivematerial within the apertures of the carrier substrate to formelectrically conductive vias and conductive bumps;

FIG. 4C is a cross-sectional representation of the semiconductor deviceof FIG. 4B, illustrating the disposal of another layer of polymericmaterial laterally adjacent the conductive bumps;

FIG. 5 is a cross-sectional representation of the semiconductor deviceof FIG. 4, illustrating contact pads disposed in communication with theconductive material of the electrically conductive vias;

FIG. 5A is a cross-sectional representation of the semiconductor deviceof FIG. 4A, illustrating contact pads disposed in communication with theconductive material of the electrically conductive vias and theconductive traces;

FIG. 6 is a cross-sectional representation of the semiconductor deviceof FIG. 5, illustrating conductive bumps disposed in communication withthe conductive material within the apertures;

FIG. 6A is a cross-sectional representation of the semiconductor deviceof FIG. 5A, depicting conductive bumps in communication with selectedones of the substantially laterally extending conductive traces;

FIG. 6B is a cross-sectional representation of the semiconductor deviceof FIG. 4C, illustrating the disposal of a layer of conductive elastomerover the conductive bumps;

FIG. 6C is a cross-sectional representation of the semiconductor deviceof FIG. 4C, illustrating the disposal of a layer of conductive elastomerincluding laterally extending conductive regions over the conductivebumps;

FIG. 6D is a cross-sectional representation of the semiconductor deviceof FIG. 6A, illustrating the disposal of another layer of polymericmaterial laterally adjacent the conductive bumps;

FIG. 7 is a schematic representation of the singulation of chip-scalepackages from a wafer including a plurality of chip-scale packages;

FIG. 8A is a cross-sectional representation of another embodiment of achip-scale package according to the present invention, which includes asemiconductor device having bond pads in a leads over chip (“LOC”) typearrangement;

FIG. 8B is a schematic representation of the top of the chip-scalepackage of FIG. 8A;

FIG. 8C is a schematic representation of the top of a variation of thechip-scale package of FIG. 8A, which includes groups of external packagebumps that correspond to single bond pads of the semiconductor device;

FIG. 8D is a cross-sectional representation of another variation of thechip-scale package of FIG. 8A, which includes a semiconductor devicehaving peripherally disposed bond pads;

FIG. 9A is a cross-sectional representation of another embodiment of thechip-scale package of the present invention, which includes asemiconductor device having peripherally disposed bond pads;

FIG. 9B is a cross-sectional representation of a variation of thechip-scale package of FIG. 9A, wherein the bond pads of thesemiconductor device are disposed in a LOC-type arrangement; and

FIGS. 10A and 10B are cross-sectional representations of anotherembodiment of the chip-scale package, wherein the carrier substrateincludes regions of conductive elastomer therethrough.

DETAILED DESCRIPTION OF THE INVENTION

With reference to FIG. 1, a preferred embodiment of a chip-scale package10 (“CSP”) according to the present invention is illustrated. Chip-scalepackage 10 includes a semiconductor device 12 and a carrier substrate 18disposed adjacent an active surface 14 of semiconductor device 12.

Semiconductor device 12 is preferably a flip-chip-type semiconductordevice, including bond pads 16 disposed on active surface 14 thereof ineither an array thereover or proximate the periphery of semiconductordevice 12. However, semiconductor devices that include peripherallylocated bond pads are also within the scope of the present invention.

Carrier substrate 18 comprises a polymeric material, such as apolyimide, and has a substantially consistent thickness. Carriersubstrate 18 includes electrically conductive vias 21, which are alsoreferred to herein as vias for simplicity, extending therethrough and incommunication and substantial alignment with their corresponding bondpads 16. As illustrated, carrier substrate 18 may also includeconductive traces 22 that extend substantially laterally from selectedones of electrically conductive vias 21 and that communicate with theircorresponding electrically conductive vias 21. These conductive traces22 extend substantially laterally from their corresponding electricallyconductive vias 21 and may be carried on a surface of carrier substrate18 opposite semiconductor device 12 or may otherwise be carried bycarrier substrate 18. Carrier substrate 18 may also have electricallyconductive bumps 24 disposed in communication with correspondingelectrically conductive vias 21. These electrically conductive bumps 24may be disposed adjacent their corresponding electrically conductivevias 21 or in contact with conductive traces 22 that correspond to theircorresponding electrically conductive vias 21. The conductive bumps 24may be disposed in direct contact with their corresponding electricallyconductive via 21 or conductive trace 22. Alternatively, conductivebumps 24 may be disposed in communication with their correspondingelectrically conductive via 21 or conductive trace 22 by means of a pad23 of ball-limiting metallurgy (“BLM”) or under-bump metallurgy (“UBM”)of a type known in the art (see FIGS. 5-6A).

FIG. 1A illustrates another embodiment of a chip-scale package 110according to the present invention. Chip-scale package 110 includes asemiconductor device 112 with bond pads 116 disposed on an activesurface 114 thereof. A carrier substrate 118 disposed adjacent activesurface 114 of semiconductor device 112 may include one or more layers118 a, 118 b of polymeric material. Apertures 120 that are definedthrough carrier substrate 118 are preferably substantially alignablewith corresponding bond pads 116 of semiconductor device 112. Eachaperture 120 preferably includes a quantity of conductive materialtherein. Each aperture 120 and the conductive material thereincollectively define an electrically conductive via 121, which may extendsubstantially through carrier substrate 118. A layer 126 of elastomer isdisposed adjacent backside 119 of carrier substrate 118. Layer 126includes conductive regions 127, such as regions of a conductiveelastomer (e.g., a z-axis elastomer) surrounded by nonconductiveelastomer 125, that correspond substantially to and are substantiallyalignable with corresponding electrically conductive vias 121 or othercorresponding electrically conductive features of carrier substrate 118.Conductive regions 127 may extend laterally beyond the peripheries oftheir corresponding electrically conductive vias 121 or otherelectrically conductive features of carrier substrate 118. Accordingly,conductive regions 127 may facilitate the electrical connection ofsemiconductor device 112 to a substrate that includes contact padsdisposed in a different footprint than that of bond pads 116 ofsemiconductor device 112. Chip-scale package 110 may also includeconductive bumps 124 adjacent conductive regions 127 of layer 126. Aprotective layer 128 may be disposed adjacent layer 126 and laterallyadjacent to any conductive bumps 124. Protective layer 128 may protectlayer 126 and provide support for conductive bumps 124.

With reference to FIG. 2, carrier substrate 18 may be disposed on activesurface 14 of semiconductor device 12 by known processes. For example, aquantity of polymeric material, such as a polyimide, an epoxy, parylene,a fluoropolymer, or a photoresist, may be disposed on active surface 14and spread to a substantially uniform thickness, in order to definecarrier substrate 18. The quantity of polymeric material may be spreadby known processes, such as by spin-on techniques or by mechanicalmeans, such as the use of a doctor blade.

Alternatively, a preformed sheet of polymeric material may be secured toactive surface 14 of semiconductor device 12. Preferably, if such apreformed sheet of polymeric material is employed as carrier substrate18, the preformed sheet is secured to active surface 14 by way of anadhesive material 18 a depicted in phantom. Alternatively, the preformedsheet of polymeric material may be heated to secure the same to activesurface 14 of semiconductor device 12.

As another alternative, the polymer of carrier substrate 18 may comprisea durable polymeric material which can be applied to a semiconductordevice in a layer having a thickness of up to about one mil (25 microns)or greater and which may be formed into desired shapes of very fineresolution (i.e., about 1 μm and lower) by photoimaging processes. Somephotoimageable epoxies are useful as the polymer of carrier substrate18. One such material is the multi-functional glycidyl ether derivativeof bisphenol-A novolac high-resolution negative photoresist availablefrom Shell Chemical Company of Houston, Tex. under the trade name EPON®SU-8. EPON® SU-8 is a low molecular weight resin which is useful forfabricating structures having dimensions in the lower range of about0.25 μm to about 0.10 μm. As employed in the present invention, however,the multi-functional glycidyl ether derivative of bisphenol-A novolac isuseful for forming layers of up to about 250 μm (10 mils) thick. Whencombined with a photoinitiator, or promoter, the photoimageable epoxyforms a highly structured, cross-linked matrix. One such photoinitiatoris triaryl sulfonium salt, which is available from Union CarbideCorporation of Danbury, Conn. under the trade name CYRACURE® UVI. Thathighly structured, cross-linked matrix may then be solvated in organicsolvents such as gamma-butyrolactone, propylene glycol methyl etheracetate, and methyl iso-butyl ketone. Other photoinitiators are alsouseful for forming such cross-linked matrices with multi-functionalglycidyl ether derivatives of bisphenol-A novolac such as EPON® SU-8.

Upon solvation of the photoimageable epoxy, a desired thickness of thephotoresist-photoinitiator compound is applied to active surface 14 ofsemiconductor device 12 by known methods, such as by spin-coating orspraying. The compound layer may be masked by known processes andcross-linked by exposure to radiation to define apertures 20therethrough. Radiation sources which are useful for cross-linkingovercoat layers which include a multi-functional glycidyl etherderivative of bisphenol-A novolac include, without limitation,ultraviolet radiation, electron-beam radiation, and X-ray radiation. Dueto the transparency of the multi-functional glycidyl ether derivative ofbisphenol-A novolac that is useful in the present invention,photoimaging of carrier substrate 18 defines apertures 20 havingsubstantially perpendicular walls. The excess material is then removedfrom the semiconductor device by known methods. Other materials,including other ultraviolet, X-ray, electron-beam, and laser-imageablematerials may be employed to fabricate carrier substrate 18. Forexample, photoimageable polyimides and other photoimageable materialswhich are not fully transparent may be used to fabricate carriersubstrate 18.

The polymeric material employed as carrier substrate 18 will preferablywithstand the temperatures and other conditions that may be subsequentlyemployed to fabricate or assemble chip-scale package 10. For example,the polymeric material of carrier substrate 18 should withstand anymetallization processes that are subsequently employed to fabricateelectrically conductive vias 21 (see FIGS. 1 and 1A), conductive traces22 (see FIGS. 1 and 1A), and any ball-limiting metallurgy such as thatof pads 23 (see FIGS. 5-6A), as well as the increased temperaturestypically associated with disposing conductive bumps, such as solderbumps, proximate thereto. The polymeric material of carrier substrate 18will also preferably maintain its integrity and otherwise withstandconditions to which carrier substrate 18 is exposed during any maskingor patterning of structures on either carrier substrate 18 orsemiconductor device 12. For example, the polymeric material of carriersubstrate 18 should withstand exposure to photomasked chemicals, as wellas any etchants to which carrier substrate 18 may be exposed.

The polymeric material of carrier substrate 18 preferably has a similarcoefficient of thermal expansion to that of the materials of activesurface 14 of semiconductor device 12 so as to minimize the likelihoodof stress related failure of the electrical links between semiconductordevice 12 and carrier substrate 18. Alternatively, the polymericmaterial of carrier substrate 18 may have a thickness that minimizes thelikelihood of such stress related failure.

Referring to FIG. 2A, the polymeric material of carrier substrate 18 mayalso be disposed adjacent a peripheral edge 15 of semiconductor device12. As an example, if a preformed film of polymeric material is employedas carrier substrate 18, portions of the film of polymeric material maybe wrapped so as to be disposed against and secured to peripheral edge15. If the polymeric material of carrier substrate 18 is spread to asubstantially uniform thickness following its disposal on active surface14 of semiconductor device 12 and semiconductor device 12 has alreadybeen singulated from a wafer, some of the polymeric material may bepermitted to flow around peripheral edge 15 and may, thereby, bedisposed adjacent peripheral edge 15.

With reference to FIG. 2B, carrier substrate 18 may be secured tosemiconductor device 12 on a wafer scale. Stated another way, a layer ofpolymeric material, which comprises carrier substrate 18, may bedisposed on a wafer 30 that includes a plurality of semiconductordevices 12 (see FIGS. 1, 2, and 2A), which wafer is also referred toherein as a semiconductor device wafer.

Referring now to FIG. 3, apertures 20 may be formed through carriersubstrate 18. Preferably, apertures 20 extend substantiallylongitudinally through carrier substrate 18 and are substantiallyalignable with corresponding bond pads 16 of semiconductor device 12.Apertures 20 may either be preformed through carrier substrate 18 byknown processes (e.g., mechanically or laser-drilled), formed aftercarrier substrate 18 has been secured to active surface 14 ofsemiconductor device 12, or defined during the fabrication of carriersubstrate 18, such as by the photoimaging processes disclosed above inreference to the use of photoimageable epoxies as carrier substrate 18.

If apertures 20 are formed through carrier substrate 18 after carriersubstrate 18 has been secured to active surface 14, known processes maybe employed to define apertures 20. For example, mask and etchtechniques may be employed to define apertures 20 through carriersubstrate 18. Alternatively, known laser-drilling processes may beemployed to define apertures 20. As another alternative, apertures 20may be defined by known mechanical drilling processes.

Referring to FIG. 4, conductive material may be disposed in each ofapertures 20 in order to define electrically conductive vias 21 throughcarrier substrate 18. Preferably, electrically conductive vias 21 areeach positioned to align substantially with a corresponding bond pad 16of semiconductor device 12. Known processes may be employed to fabricateelectrically conductive vias 21. For example, a quantity of conductivematerial, such as a metal, may be disposed over carrier substrate 18,including within the apertures 20 thereof. The conductive material maybe disposed on a backside 19 of carrier substrate 18 by known processes,such as by physical vapor deposition (“PVD”) (e.g., sputtering) orchemical vapor deposition (“CVD”) processes. As these processestypically blanket deposit a layer of conductive material onto a surface,it may be necessary to pattern the layer of conductive material. Knowntechniques, such as the use of a photomask and etching processes, may beemployed to remove conductive material substantially from backside 19 ofcarrier substrate 18.

Turning now to FIG. 4A, conductive traces 22, which extend substantiallylaterally from selected ones of electrically conductive vias 21, may befabricated so as to be carried by carrier substrate 18. Preferably,these conductive traces 22 are disposed on backside 19 of carriersubstrate 18. Alternatively, conductive traces 22 may extend, at leastpartially, internally through carrier substrate 18. Each conductivetrace 22 preferably communicates with a corresponding electricallyconductive via 21 of carrier substrate 18 and, therefore, with acorresponding bond pad 16 of semiconductor device 12. Since conductivetraces 22 extend substantially laterally from their correspondingelectrically conductive vias 21, conductive traces 22 of carriersubstrate 18 are useful for establishing electrical connections betweenthe contacts of a substrate and bond pads 16 of a semiconductor device12 having a different footprint than that of substrate 18.

If electrically conductive vias 21 were fabricated by a technique thatemployed a blanket-deposited layer of conductive material, conductivetraces 22 may be defined from the layer of conductive material as thelayer of conductive material is patterned to define electricallyconductive vias 21. Alternatively, conductive traces 22 may befabricated at a different time than when electrically conductive vias 21are fabricated. Again, conductive traces 22 may be fabricated by knownprocesses, such as by disposing a layer of conductive material onbackside 19 of carrier substrate 18 and removing selected regions of thelayer of conductive material to pattern the same and to defineconductive traces 22 therefrom. Known mask and etch processes may beemployed to pattern the conductive layer.

Alternatively, with reference to FIG. 4B, which illustrates thefabrication of package 110, electrically conductive vias 121 may befabricated by disposing the solder within apertures 120. Solder may bedisposed within apertures 120 by known processes, such as by wave solderprocesses, by disposing a molten solder ball adjacent or in eachaperture 120, or by disposing a solder brick within or adjacent to eachaperture 120 and heating the solder brick to reflow the same.Preferably, as molten solder is disposed within each aperture 120, anelectrically conductive via 121 is formed and substantially concurrentlybonded to a corresponding bond pad 116 of semiconductor device 112.

When solder is employed as the conductive material of electricallyconductive vias 121, if the solder protrudes beyond backside 119 ofcarrier substrate 118, it may be necessary to dispose an additionalquantity of polymeric material on backside 119. As illustrated in FIG.4C, a second substrate layer 118 b may be disposed on backside 119 ofcarrier substrate 118. Second substrate layer 118 b may be disposed byknown processes, such as by the processes explained above in referenceto FIGS. 2 and 2A. Subsequent processes may then be performed on abackside 119 b of second substrate layer 118 b, including thoseprocesses that are explained in reference to backside 119 of carriersubstrate 118.

With reference to FIGS. 5 and 5A, a pad 23, 23′ may be fabricated incontact or otherwise in communication with a corresponding electricallyconductive via 21 or conductive trace 22. If such a pad 23, 23′ isemployed, the use of known ball-limiting metallurgy (“BLM”) orunder-bump metallurgy (“UBM”) structures is preferred. Pad 23, 23′ maybe fabricated by known processes, such as the processes that aretypically employed to fabricate ball-limiting metallurgy structures(e.g., fabricating layers by PVD and patterning the layers by mask andetch processes). Accordingly, each pad 23, 23′ may include an adhesionlayer adjacent the conductive material of its corresponding electricallyconductive via 21 or conductive trace 22, a solder wetting layeradjacent the adhesion layer, and an exposed, substantially nonoxidizableprotective layer (e.g., gold or other noble metal) adjacent the solderwetting layer.

FIGS. 8A and 8B illustrate another embodiment of a chip-scale package210, which includes a semiconductor device 212 and a carrier substrate218 disposed adjacent an active surface 214 of semiconductor device 212.

As illustrated, semiconductor device 212 is a leads over chip (“LOC”)type semiconductor device, which includes bond pads 216 disposedsubstantially linearly across the center of semiconductor device 212. Aconductive bump 217 may be disposed on each bond pad 216 or on a BLM orUBM structure adjacent to each bond pad 216.

Carrier substrate 218 comprises an insulative layer 220, preferablyformed of polymeric material, such as polyimide or another nonconductiveelastomer, and has a substantially consistent thickness. Bond pads 216of semiconductor device 212 or conductive bumps 217 are exposed throughlayer 220 through one or more apertures 228. An adhesive film layer 230is disposed adjacent layer 220, opposite semiconductor device 212.Adhesive film layer 230 carries conductive traces 222 and externalpackage bumps 224. External package bumps 224 protrude from adhesivefilm layer 230. Conductive traces 222 are in electrical communicationwith corresponding external package bumps 224 and extend across adhesivefilm layer 230 to corresponding vias 221. Vias 221, which communicatewith conductive traces 222, extend through adhesive film layer 230, intoapertures 228, and into electrical communication with corresponding bondpads 216.

As illustrated in FIGS. 8A and 8B, each conductive trace 222communicates with a corresponding external package bump 224. Thus, eachbond pad 216 that communicates with a conductive trace 222 may alsocommunicate with a laterally offset, corresponding external package bump224. Alternatively, as illustrated in FIG. 8C, each conductive trace 222may communicate with a group or an array of external package bumps 224′.

FIG. 8D illustrates a variation of chip-scale package 210′, whichincludes a semiconductor device 212′ having peripherally located bondpads 216′ and external package bumps 224′ disposed in an array onadhesive film layer 230′.

With reference to FIG. 9A, another embodiment of a chip-scale package310 according to the present invention is illustrated. Chip-scalepackage 310 includes a semiconductor device 312 having bond pads 316disposed on an active surface 314 of semiconductor device 312, adjacentthe periphery thereof. Selected bond pads 316 have conductive bumps 317adjacent thereto.

A carrier substrate 318 is disposed adjacent active surface 314. Carriersubstrate 318 includes an insulative layer 320, preferably formed of anelectrically nonconductive polymeric material, such as polyimide oranother elastomer, and has a substantially uniform thickness. Insulativelayer 320 includes apertures 328 formed therethrough to receiveconductive bumps 317. Preferably, conductive bumps 317 have a heightsubstantially equal to or greater than the thickness of insulative layer320.

An adhesive film layer 330 is disposed adjacent insulative layer 320,opposite semiconductor device 312. Adhesive film layer 330 carrieselectrically conductive traces 322 and external package bumps 324, whichprotrude from adhesive film layer 330. Electrically conductive traces322 are disposed across adhesive film layer 330 so as to extend between,to electrically contact, and to facilitate electrical communicationbetween a conductive bump 317 and one or more corresponding externalpackage bumps 324.

FIG. 9B illustrates a variation of chip-scale package 310′, wherein thesemiconductor device 312′ is a LOC-type device having bond pads 316′disposed substantially linearly across the center of the active surface314′ thereof.

FIGS. 9A and 9B illustrate chip-scale packages 310, 310′ that rearrangethe peripheral and LOC-type footprints of semiconductor devices 312,312′ to provide array-type footprints of external package bumps 324,324′.

The chip-scale packages 210, 210′, 310, 310′ illustrated in FIGS. 8A-9Band the features thereof may be fabricated by processes that are knownin the art, such as by the processes described above with reference toFIGS. 1-5A.

Referring now to FIGS. 6 and 6A, conductive bumps 24 may be disposed incontact or otherwise in communication with electrically conductive vias21 or conductive traces 22. If carrier substrate 18 includes any pads23, 23′, conductive bumps 24 are preferably disposed adjacent such pads23, 23′. Conductive bumps 24 may comprise any electrically conductivematerial known in the art to be useful as a conductive joint betweenadjacent devices. Exemplary materials include, without limitation,solders, electrically conductive elastomers (e.g., z-axis elastomers),z-axis tapes, and other electrically conductive materials andstructures. Known processes may be employed to fabricate conductivebumps 24 from these materials and in communication with selected ones ofelectrically conductive vias 21 of carrier substrate 18.

Alternatively, with reference to FIGS. 6B and 6C, which illustrate thefabrication of package 110, if carrier substrate 118 does not includeconductive traces extending across backside 119 thereof or if only acontact region (see, e.g., reference 22 a of FIG. 1) of each conductivetrace (see, e.g., reference 22 of FIG. 1) of carrier substrate 118 isexposed to backside 119, a substantially planar layer 126 comprising anonconductive elastomer 125 having therein localized conductive regions127 of a conductive elastomer, such as a z-axis elastomer or anisotropicconductive elastomer of a type known in the art, may be disposedadjacent backside 119 of carrier substrate 118. The conductive regions127 of such a substantially planar layer 126 preferably contact eachelectrically conductive via 121 or contact region (see, e.g., reference22 a of FIG. 1) of a conductive element (not shown in FIG. 6A or 6B) tofacilitate the transmission of electrical signals through eachelectrically conductive via 121 of carrier substrate 118 to or from bondpads 116. Substantially planar layer 126 may be disposed on backside 119of carrier substrate 118 by known processes, such as by securing apreformed layer of elastomer having conductive regions 127 therein tobackside 119. Alternatively, a quantity of nonconductive elastomer 125may be disposed on backside 119 and spread to a substantially uniformthickness thereacross by known techniques, such as by spin-on processesor mechanical processes (e.g., the use of a doctor blade), electricallyconductive vias 121 exposed through nonconductive elastomer 125, and anelectrically conductive elastomer disposed adjacent electricallyconductive vias 121 so as to form conductive regions 127 peripherallysurrounded by nonconductive elastomer 125. The conductive components ofa conductive elastomer disposed in this manner may also be aligned byknown processes, such as by magnetically aligning the conductivecomponents.

Of course, with reference to FIG. 6C, conductive regions 127 ofsubstantially planar layer 126 may extend laterally beyond theperipheries of their corresponding electrically conductive vias 121 orbeyond the contact regions of their corresponding conductive traces(see, e.g., reference 22 of FIG. 1).

With reference to FIG. 6D, a protective layer 28 of polymeric materialmay be disposed adjacent backside 19 of carrier substrate 18 andlaterally adjacent conductive bumps 24 protruding therefrom. Protectivelayer 28 may also be disposed laterally adjacent or cover conductivetraces 22. Protective layer 28 preferably provides lateral support forconductive bumps 24. Known processes may be employed to disposeprotective layer 28 on backside 19 of carrier substrate 18, such asdisposing a quantity of polymeric material on backside 19 and permittingthe polymeric material to flow around conductive bumps 24 such thatconductive bumps 24 remain exposed through protective layer 28.Alternatively, protective layer 28 may be disposed in a substantiallyuniform thickness on backside 19 of carrier substrate 18 by spin-onprocesses. Materials that may be employed as protective layer 28include, without limitation, polyimides and photoresist materials.

As the chip-scale packages 10 of the present invention may be fabricatedon a wafer scale, as depicted in FIG. 2B, testing, probing, or burn-inof each of the semiconductor devices 12 of wafer 30 can be performedafter packaging, but while the semiconductor devices are still in waferform. Thus, the packaging method of the present invention eliminates theneed to individually align individually packaged semiconductor deviceswith test equipment.

FIGS. 10A and 10B illustrate an embodiment of chip-scale package 410wherein a carrier substrate 418 includes an insulative layer 430 of amaterial such as polyimide or another elastomer disposed adjacent anactive surface 414 of a semiconductor device 412.

Apertures 428 are formed through insulative layer 430 by knownprocesses, such as by the etching, laser-drilling, or other processesdisclosed above with reference to FIGS. 1-6D, to exposed bond pads 416of semiconductor device 412. Of course, the processes that are employedto form apertures 428 and the sequence in which these processes areperformed (i.e., before or after insulative layer 430 is disposed onsemiconductor device 412) depend upon the type of material or materialsfrom which insulative layer 430 is fabricated.

A quantity of conductive elastomer 421, such as a z-axis conductiveelastomer, is disposed within each aperture 428 to facilitate theelectrical communication of each bond pad 416 with a structurepositioned on an opposite side of or carried by carrier substrate 418.For example, as illustrated in FIG. 10B, a BLM or UBM pad 440 may bedisposed adjacent conductive elastomer 421. An external package bump 424may then be disposed in contact with pad 440. Alternatively, conductivetraces that communicate with external package bumps may be disposed inelectrical communication with conductive elastomer 421 so as to offsetor rearrange the footprint of semiconductor device 412.

Turning now to FIG. 7, individual chip-scale packages 10 may besingulated from wafer 30 by known singulation processes, such as by theuse of a wafer saw 40.

Although the foregoing description contains many specifics and examples,these should not be construed as limiting the scope of the presentinvention, but merely as providing illustrations of some of thepresently preferred embodiments. Similarly, other embodiments of theinvention may be devised which do not depart from the spirit or scope ofthe present invention. The scope of this invention is, therefore,indicated and limited only by the appended claims and their legalequivalents, rather than by the foregoing description. All additions,deletions and modifications to the invention as disclosed herein andwhich fall within the meaning of the claims are to be embraced withintheir scope.

1. A carrier for use in a chip-scale package, comprising: a preformedfilm, the preformed film including a first surface configured to bedisposed in substantial contact with an active surface of asemiconductor device; at least one conductive via extendingsubstantially longitudinally through the preformed film prior toplacement thereof upon the active surface of the semiconductor device,electrically exposed at the first surface of the preformed polymericfilm; and at least one contact at a second surface of the preformed filmand in communication with the at least one conductive via, and the atleast one contact and the at least one conductive via being positionedto align with at least one bond pad of the semiconductor device.
 2. Thecarrier of claim 1, wherein the preformed film comprises a polymer. 3.The carrier of claim 1, wherein the at least one conductive viacomprises a conductive bump.
 4. The carrier of claim 3, wherein theconductive bump comprises solder.
 5. The carrier of claim 3, wherein theconductive bump also forms the at least one contact.
 6. The carrier ofclaim 5, wherein the conductive bump comprises solder.
 7. The carrier ofclaim 1, further comprising: at least another conductive via extendingsubstantially through the preformed film and corresponding to at leastanother bond pad of the semiconductor device; and at least anothercontact corresponding to the at least another conductive via at thesecond surface of the preformed film and positioned to align with the atleast another bond pad of the semiconductor device.
 8. The carrier ofclaim 7, wherein the at least another conductive via is laterally offsetrelative to the at least another bond pad.
 9. The carrier of claim 7,further comprising: at least one conductive trace extending laterallybetween the at least another conductive via and the at least anothercontact.
 10. The carrier of claim 1, wherein the at least one conductivevia is configured to directly contact the at least one bond pad.
 11. Achip-scale package, comprising: a carrier including at least oneaperture extending substantially longitudinally therethrough; and asemiconductor device including an active surface having at least onebond pad thereon, the at least one bond pad electrically exposed throughthe carrier by way of the at least one aperture, an activesurface-abutting surface of the carrier in substantial contact with theactive surface and secured thereto with adhesive material disposedbetween the carrier and the active surface.
 12. The chip-scale packageof claim 11, wherein the at least one aperture and the at least one bondpad are substantially aligned.
 13. The chip-scale package of claim 11,further comprising: conductive material within the at least oneaperture.
 14. The chip-scale package of claim 13, wherein the conductivematerial communicates with the at least one bond pad.
 15. The chip-scalepackage of claim 13, wherein the conductive material contacts the atleast one bond pad.
 16. The chip-scale package of claim 15, wherein theconductive material comprises solder.
 17. The chip-scale package ofclaim 15, wherein the conductive material forms a conductive bump. 18.The chip-scale package of claim 15, wherein the conductive materialforms a contact.
 19. The chip-scale package of claim 15, furthercomprising a conductive elastomer disposed over the conductive material.20. The chip-scale package of claim 19, further comprising at least oneconductive bump disposed on the conductive elastomer, opposite theconductive material, and in communication therewith.
 21. The chip-scalepackage of claim 13, further comprising: a contact located over the atleast one aperture and in communication with the conductive materialtherein.
 22. The chip-scale package of claim 21, further comprising: aconductive structure secured to the contact.
 23. The chip-scale packageof claim 22, wherein the conductive structure comprises a conductivebump.
 24. The chip-scale package of claim 23, wherein the conductivebump comprises solder.
 25. The chip-scale package of claim 11, whereinthe carrier comprises a polymeric carrier.
 26. The chip-scale package ofclaim 11, wherein the carrier at least partially contacts a peripheraledge of the semiconductor device.